Thus, the master 68HC11 has only one input, MISO, which is the slave QVGA Controller’s only output. If the 68HC11 is initialized as a master (by setting the MSTR bit in the SPCR control register as explained below) then bit 5 of the Port D data direction register (DDRD) determines whether /SS is an input or an output. Setting SPE (SPI enable) to 1 turns on the SPI system. After configuring the SPI system to communicate on a properly connected network of devices, sending and receiving data is as simple as writing and reading a register. The entire daisy chain network is ultimately connected to a PLC (Programmable Logic Controller), facilitating data exchange between multiple devices and the central control system. Given a properly wired network and a properly configured SPCR control register, a master device may transmit a message by simply storing the byte to the SPDR data register. At any given time, only the master and a single "active" slave communicate.
The GROUND line serves as a common voltage reference for the master and slave. A ground connection is also necessary to ensure that the communicating devices have a common voltage reference. Now, why don’t companies just use USB or ethernet to transmit data between their devices? The image below explains why. It provides a convenient means of connecting the QVGA Controller to a variety of peripheral devices, including analog to digital and digital to analog converters, real time clocks, and other computers which use high speed communication. This ability to exchange messages means that the SPI is capable of full duplex communication. RS485 is highlighted for its great features: it can both send and receive messages (half-duplex), work over long distances, and resist interference. The byte-sized messages are transmitted and received via the MOSI (master out/slave in) and MISO (master in/slave out) pins. This allows the processor that is master to control the input /SS pins of other CPU’s, for example. Clearing the MSTR bit in the SPCR control register automatically configures the /SS (slave select) pin as an input. If the /SS pin of the master is an input and if a low input level is detected, the processor sets the MODF bit in the SPI status register a "mode fault" condition.
Once the data has been exchanged, a flag bit in the SPSR status register is set to indicate that the transfer is complete. Initializing the 68HC11 as a slave (by clearing the MSTR bit in the SPCR control register as explained below) automatically configures the /SS pin as an input. DH 485 is a proprietary communications protocol used by Allen-Bradley in their line of industrial control units. The 68HC11 allows the details of the synchronous communications protocol to be customized for compatibility with a variety of peripherals. This signal synchronizes the exchange of bytes between the 68HC11 processor and the peripherals. This phenomenon will appear as ringing on the edges of the signal. The one you choose depends on the specific device, or devices you will be connecting to. Transmissions are always initiated by the master device, and consist of an exchange of bytes. The SCK pin clocks the serial A/D’s CLK input which causes the A/D’s conversion result to be transferred to the master via the MISO line. The /SS pin can be configured as either an input or an output. If the /SS input to a slave is active (low), the slave transfers data in response to the SCK clock input that is initiated by the master.
The distinction between master and slave is an important one. Note that the data is changed by the transmitting device one half clock cycle before it is valid. Regardless of the network, however, there are only four signals used: SCK provides a synchronized clock, MOSI and MISO signals are used for data transmission and reception, and /SS configures the 68HC11 as a master or slave device. When the 68HC11 controls the network, it is referred to as a "master"; otherwise, it is a "slave". Even though the MOSI pin is not connected to anything, the master initiates a transmission using a "dummy" byte. The only difference between the master and slave devices is that the master initiates the transmission. It may be that only the byte sent from the master to the slave is meaningful; nevertheless, each device simultaneously transmits and receives one byte. Note that the master device outputs the clock synchronization signal SCK to the slave’s SCK which is configured as an input. In this example, the QVGA Controller selects the serial A/D by outputting a LOW signal on /SS. By setting this output LOW, the slave’s input /SS is pulled LOW. Any required SPI output signals must be configured as outputs by setting the appropriate bits in the Port D data direction register which is named PORTD.DIRECTION in the QED-Forth kernel.
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